The characteristics such as a threshold value of an element, such as a transistor, included in a semiconductor device often vary depending on process conditions. Such characteristic variations may occur not only between lots but also in the same wafer, and to know its trend gives essential data to enhance yield of products.
As a method for grasping characteristic variations of an element, a method is known for providing a plurality of TEGs (Test Element Groups) on a wafer. Since the TEGs are arranged normally on a scribe line of a wafer, they do not remain on the chip after dicing. Due to this, an increase in the area of the chip does not occur due to the TEGs.
FIG. 6 is a schematic diagram showing an exemplary arrangement of the TEGs on a wafer.
In the example shown in FIG. 6, the TEGs are arranged at five positions of a wafer 10. More specifically, one of them is arranged approximately at the center of the wafer 10 and the others are arranged at the upper, lower, left-hand, and right-hand positions, respectively. The reason that the TEGs are arranged dispersedly in such a manner is to grasp the characteristic variations in the plane of the wafer 10. There are, however, various patterns of variations in the plane of the wafer 10 and, for example, the pattern can be doughnut-shaped as shown in FIG. 7. In FIG. 7, the threshold value of a transistor is high in a region 11, and the threshold value of a transistor is low in a region 12.
Consequently, when variations in the plane shown in FIG. 7 occur, the variations cannot be grasped by the five TEGs. In other words, in the example shown in FIG. 7, all of the five TEGs are located in the region 12 having a low threshold value and therefore the presence of the doughnut-shaped region 11 having a high threshold value cannot be recognized. One solution to this is to increase the number of arranged TEGs, while a problem arises in this case that it takes a long time to measure the TEGs. In addition, jigs for measurement will become more complex.
Further, as described above, since the TEGs are arranged on the scribe line of the wafer, there is a problem that the measurement is not available after dicing has been performed. These problems are solved by providing the TEG for each chip in the wafer. However, since the TEG requires a dedicated measuring pad, the chip area will increase considerably if the TEG is provided for each chip.
As conventional technologies relating to testing of a semiconductor device, technologies described in Japanese Patent Application Laid-opens Nos. H09-186565, H10-115672, H11-340806, and 2004-171730 are known.